Giovanni Agosta

Dipartimento di Elettronica e Informazione
P.za Leonardo da Vinci, 32
20133 Milano, Italia
Stanza 127, I Piano
Tel. +39 02 2399 3550
Fax. +39 02 2399 4311

Birthdate: December 28th, 1975
Birthplace: Roma, Italy
Italian Nationality
Native language: Italian
Foreign languages: English at the TOEFL level 597 (paper-based test); basic knowledge of French

I currently hold the position of Ricercatore (researcher with tenure/assistant professor) at Politecnico di Milano, within the Dipartimento di Elettronica e Informazione (department of electronics and information technology). My research interests focus on the interaction between compiler and architecture, including dynamic compilation for embedded systems, power-aware compilation, and compiler technology for many-core architectures. I have also a strong interest towards design methodologies for embedded systems, including cryptographic applications, as well as the theoretical foundations of logic synthesis. Therefore, I participate in both the Advanced software architectures and methodologies (more specifically, in the Formal Languages and Compilers group) and the System Architectures research lines within the Computer Science and Engineering section of the department.

Ph.D. studies in Information Technology (focus on Computer Science and Engineering) at Politecnico di Milano.

My major research focused on Dynamic Compilation for ILP Architectures. The research advisor was Professor Stefano Crespi Reghizzi, of Dipartimento di Elettronica e Informazione, Politecnico di Milano.

The minor research project was in the area of hardware/software co-design. The work focused on SystemC Specifications for Hardware/Software Partitioning. Advisor for this research area was Professor Donatella Sciuto, of Dipartimento di Elettronica e Informazione, Politecnico di Milano.

Engineering studies at Politecnico di Milano, where I obtained the laurea degree in Ingegneria Informatica (Computer Engineering, 5-years MS+BS program).

In 1999-2000 I have worked on my thesis at ST Microelectronics Labs at Agrate, on a research project on compilation and instruction scheduling for high-performance microprocessors. My main assignment has been to design and implement an algorithm for parallelizing C code to be compiled for a cluster of ILP processors.

The thesis advisor was Professor Stefano Crespi Reghizzi, and co-advisor was Rinaldo Poluzzi of STMicroelectronics.

High-school education at Lycée G. Parini of Milan, a leading humanities oriented institution.

1. G. Agosta, S. Crespi Reghizzi, G. Falauto, and M. Sykora. Just-In-Time Scheduling Translation for Parallel Processors. In Scientific Programming, Vol 13, No 3, IOS Press, 2005. (pdf draft)
2. G. Agosta, G. Palermo and C. Silvano. Efficient Architecture/Compiler Co-Exploration Using Analytical Models. In Design Automation for Embedded Systems, Vol 11, No 1, Mar 2006, Springer. (pdf draft)
3. G. Agosta, L. Breveglieri, G. Pelosi and M. Sykora. Programming Highly Parallel Reconfigurable Architectures for Symmetric and Asymmetric Cryptographic Applications. In Journal of Computers, Vol 2, No 8, 2007, Academy Publisher. (pdf draft)
4. G. Agosta, F. Bruschi and D. Sciuto. Static Analysis of Transaction Level Communication Models. In IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, volume 27, issue 8, pages 1412-1424, August 2008 (accepted April 2008). (pdf draft)
5. G. Agosta, F. Bruschi, G. Pelosi and D. Sciuto. A Transform-Parametric Approach to Boolean Matching. In IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, volume 28, issue 6, pages 805-817, June 2009 (accepted January 2009). (pdf draft)
6. S. Campanoni, G. Agosta, S. Crespi Reghizzi and A. Di Biagio. A highly flexible, parallel virtual machine: design and experience of ILDJIT. In Software: Practice and Experience, Volume 40 Issue 2, pages 177-207, January 2010 (accepted June 2009). (pdf draft)
7. A. Di Biagio, G. Agosta, C. Silvano, M. Sykora. Architecture Optimization of Application-Specific Implicit Instructions. In ACM Transaction on Embedded Computing Systems, Volume 11 Issue S2, August 2012 Article No. 44 (accepted January 2010).
8. G. Agosta, M. Bessi, E. Capra and C. Francalanci. Automatic memoization for energy efficiency in financial applications. In Sustainable Computing: Informatics and Systems, Volume 2, Issue 2, June 2012, Pages 105–115 (accepted January 2012).
9. G. Agosta, A. Barenghi, A. Di Federico, and G. Pelosi. OpenCL Performance Portability for GPGPUs: an Exploration on Cryptographic Primitives. In Concurrency and Computation: Practice and Experience volume 27, number 14(accepted July 2014, published online August 2014, in print September 2015).
10. G. Agosta, A. Barenghi, M. Maggi, and G. Pelosi. Design Space Extension for Secure Implementation of Block Ciphers. In IET Computers & Digital Techniques (accepted September 2014, published online October 2014).
11. G. Agosta, A. Barenghi, G. Pelosi, and M. Scandale. Trace-based Schedulability Analysis to Enhance Passive Side-Channel Attack Resilience of Embedded Software. In Information Processing Letters, Elsevier (accepted September 2014, published online October 2014, published on paper February 2015).
12. G. Agosta, A. Barenghi, G. Pelosi, and M. Scandale. The MEET Approach: Securing Cryptographic Embedded Software against Side Channel Attacks. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume PP, issue 99, http://dx.doi.org/10.1109/TCAD.2015.2430320 (accepted April 2015, published August 2015).
13. A. Oleksiak, M. Kierzynka, W. Piatek, G. Agosta, A. Barenghi, C. Brandolese, W. Fornaciari, G. Pelosi, M. Cecowski, R. Plestenjak, J. Činkelj, M. Porrmann, J. Hagemeyer, R. Griessl, J. Lachmair, M. Peykanu, L. Tigges, M. vor dem Berge, W. Christmann, S. Krupop, A. Carbon, L. Cudennec, T. Goubier, J.-M. Philippe, S. Rosinger, D. Schlitt, C. Pieper, C. Adeniyi-Jones, J. Setoain, L. Ceva, U. Janssen, M2DC – Modular Microserver DataCentre with Heterogeneous Hardware, Microprocessors and Microsystems, Available online 3 June 2017, ISSN 0141-9331, https://doi.org/10.1016/j.micpro.2017.05.019. (online)
14. S. Cherubin and G. Agosta. LibVersioningCompiler: an easy-to-use library for dynamic generation and invocation of multiple code versions. In Software X, 7:95-100, 2018, Elsevier.
15. G. Agosta, A. Barenghi, G. Pelosi, and M. Scandale. Reactive Side-channel Countermeasures: Applicability and Quantitative Security Evaluation. Microprocessors & Microsystems, 2018. accepted July 4, 2018.
16. A. Balador, A. Kouba, D. Cassioli, F. Foukalas, R. Severino, D. Stepanova, G. Agosta, J. Xie, L. Pomante, M. Mongelli, P. Pierini, S. Petersen, and T. Sukuvaara. Wireless Communication Technologies for Safe Cooperative Cyber Physical Systems. Sensors, 18, 2018.
17. J. Flich, G. Agosta, et al. MANGO: exploring Manycore Architectures for Next-GeneratiOn HPC systems. Microprocessors & Microsystems, 61:154 – 170, 2018.
18. G. Agosta, A. Barenghi, and G. Pelosi. Compiler-based techniques to secure cryptographic embedded software against side channel attacks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1–5, 2019.
19. S. Cherubin, D. Cattaneo, M. Chiari, A. Di Bello, and G. Agosta. TAFFO: Tuning assistant for floating to fixed point optimization. IEEE Embedded Systems Letters, pages 1–4, 2019.

1. G. Agosta, F. Bruschi and D. Sciuto. UML Tailoring for SystemC and ISA Modelling. In UML for SoC Design, Chapter 7, pages 147-173, Springer, Jul 2005. (pdf draft)
2. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Huebert , B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf , G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mahonen, and B. Vanthournout. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. In Designing Very Large Scale Integration Systems: Emerging Trends & Challenges, Springer Netherlands, August 31, 2011, ISBN 978-94-007-1487-8.
3. G. Agosta, M. Cartron, and A. Miele. Fault Tolerance. In Smart Multicore Embedded Systems, pages 81-101, Springer, Jan 2014, ISBN 978-1-4614-8800-2.
4. G. Agosta, A. Barenghi, G. Pelosi, and M. Scandale. Symmetric Key Encryption Acceleration on Heterogeneous Many-Core Architectures. In Practical Cryptography: Algorithms and Implementations Using C++, pages 251-297, CRC Press, Dec 2014, ISBN 978-1-4822-2889-2.
5. A. Oleksiak, M. Kierzynka, W. Piatek, M. Vor Dem Berge, W. Christmann, S. Krupop, M. Porrmann, J. Hagemeyer, R. Griessl, M. Peykanu, L. Tigges, S. Rosinger, D. Schlitt, C. Pieper, U. Janssen, G. Agosta, C. Brandolese, W. Fornaciari, G. Pelosi, M. Cecowski, R. Plestenjak, J. Cinkelj, L. Cudennec, T. Goubier, J.-M. Philippe, C. Adeniyi-Jones, L. Ceva, and H. Rauchfuss. M2DC – Modular Microserver DataCentre with Heterogeneous Hardware. In Data Center Accelerators for Cloud Computing, pages 109–128. Springer publication, 2018.

1. G. Agosta, F. Bruschi and D. Sciuto. Static Analysis of Transaction-Level Models. In 40th Annual ACM/IEEE Design Automation Conference (DAC'03), June 2003.
2. G. Agosta, F. Bruschi, and D. Sciuto. Synthesis of Dynamic Class Loading Specifications on Reconfigurable Hardware. In 2nd IEEE International Workshop on Electronics Design, Test and Applications (DELTA 2004), Jan 2004.
3. G. Agosta, G. Palermo, and C. Silvano. Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architectures for Low-Power Embedded Systems. In 19th Annual ACM Symposium on Applied Computing, Special Track on Embedded Systems, Mar 2004.
4. G. Agosta, S. Crespi Reghizzi, G. Falauto, and M. Sykora. Just-In-Time Scheduling Translation for Parallel Processors. In Third International Symposium on Parallel and Distributed Computing, Jul 2004.
5. G. Agosta, F. Bruschi, M. Santambrogio and D. Sciuto. A Data Oriented Approach to the Design of Reconfigurable Stream Decoders. In IEEE 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, New York, Sep 2005.
6. G. Agosta, F. Bruschi and D. Sciuto. Aspect Orientation in System Level Design. In Forum on specification & Design Languages, Lausanne, Sep 2005.
7. G. Agosta, S. Crespi Reghizzi, P. Palumbo and M. Sykora. Selective Compilation via Fast Code Analysis and Bytecode Tracing. In proceedings of the 21st Annual ACM Symposium on Applied Computing, Dijon, Apr 2006.
8. G.Agosta, F. Bruschi, M. Santambrogio and D. Sciuto. Synthesis of Object Oriented Models on Reconfigurable Hardware. In The 2006 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Jun 2006.
9. G. Agosta, M. Santambrogio and S. Ogrenci Memik. Adaptive Metrics for System-Level Functional Partitioning. In proceedings of the Forum on specification & Design Languages, Darmstadt, Sep 2006.
10. G. Agosta, S. Crespi Reghizzi and G. Svelto. Jelatine: A Virtual Machine for small embedded systems. In proceedings of the 4th Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2006), Paris, Oct 2006.
11. G. Agosta, S. Crespi Reghizzi, D. Domizioli and M. Sykora. Global Instruction Scheduling in Dynamic Compilation for Embedded Systems. In proceedins of the 4th Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2006), Paris, Oct 2006.
12. G. Agosta, L. Breveglieri, G. Pelosi and M. Sykora. Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications. In proceedings of the 4th International Conference on Information Technology : New Generations (ITNG 2007), Las Vegas, Apr 2007. (pdf)
13. G. Agosta, F. Bruschi and D. Sciuto. An Efficient Cost-Based Canonical Form for Boolean Matching. In proceedings of the 17th ACM Great Lakes Symposium on VLSI, Stresa, Mar 2007.
14. G. Agosta, F. Bruschi, G. Pelosi and D. Sciuto. A Unified Approach to Canonical Form-based Boolean Matching. In proceedings of the 44th Annual ACM/IEEE Design Automation Conference (DAC'07), June 2007.
15. G. Agosta, L. Breveglieri, I. Koren and G. Pelosi. Countermeasures for Branch Target Buffer Attacks. In proceedings of the 4th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2007), Wien, Sep 2007. (pdf)
16. G. Agosta and G. Pelosi. A Domain Specific Language for Cryptography. In proceedings of the Forum on specification and Design Languages (FDL 07), Barcelona, Sep 2007. (pdf)
17. G. Agosta, C. Silvano and M. Sykora. Dynamic Configuration of Application-Specific Implicit Instructions for Embedded Pipelined Processors. In proceedings of the 23rd ACM Symposium on Applied Computing, Fortaleza, Mar 2008. (Best Paper Award)
18. S. Campanoni, G. Agosta and S. Crespi Reghizzi. ILDJIT: A parallel dynamic compiler for CIL bytecode. In Proceedings of the 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Rhodes, Oct 2008. (pdf)
19. S. Campanoni, M. Sykora, G. Agosta and S. Crespi Reghizzi. Dynamic Lookahead Compilation. In Proceedings of the 12th Compiler Construction conference (CC 2009), York, Mar 2009.
20. A. Di Biagio, A. Barenghi, G. Pelosi and G. Agosta. Design of a Parallel AES for Graphics Hardware using the CUDA framework. In proceedings of the 5th International Workshop on Security in Systems and Networks (SSN2009, associated with IPDPS 2009), Rome, May 2009. (pdf draft)
21. M. Tartara, S. Campanoni, G. Agosta and S. Crespi Reghizzi. Just-In-Time compilation on ARM processors. In proceedings of the fourth workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems (ICOOOLPS 2009), Genova, July 2009.
22. G. Agosta, A. Barenghi, A. Di Biagio, F. De Santis, G. Pelosi. Fast Disk Encryption Through GPGPU Acceleration. In Proceedings of The Tenth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2009), Hiroshima, December 2009. (pdf draft)
23. A. Di Biagio and G. Agosta. Improved Programming of GPU Architectures through Automated Data Allocation and Loop Restructuring. In Proceedings of the 2PARMA Workshop (ARCS2010 Workshop), Hannover, February 2010.
24. M. Tartara, S. Campanoni, G. Agosta and S. Crespi Reghizzi. Parallelism and Retargetability in the ILDJIT Dynamic Compiler. In Proceedings of the 2PARMA Workshop (ARCS2010 Workshop), Hannover, February 2010.
25. G. Agosta, A. Barenghi, F. De Santis and G. Pelosi. Record Setting Software Implementation of DES Using CUDA. In proceedings of the 7th International Conference on Information Technology : New Generations (ITNG 2010), Las Vegas, April 2010. (pdf draft)
26. E. Speziale, A Di Biagio, and G. Agosta. An Optimized Reduction Design to Minimize Atomic Operations in Shared Memory Multiprocessors. In proceedings of the 16th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2011, associated with IPDPS 2011), Anchorage, May 2011.
27. G. Agosta, M. Bessi, E. Capra and C. Francalanci. Dynamic Memoization for Energy Efficiency in Financial Applications. In proceedings of the Second International Green Computing Conference (IGCC'11), Orlando, July 2011.
28. A. Di Biagio, E. Speziale, G. Agosta. Exploiting Thread-Data Affinity in OpenMP with Data Access Patterns. In proceedings of Euro-Par 2011, Bordeaux, August/September 2011.
29. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J.M. Zins, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout. Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach. In proceedings of IEEE INDIN, Lisbon, July 2011.
30. G. Agosta, A. Barenghi, G. Pelosi. High speed cipher cracking: the case of Keeloq on CUDA. In 3rd Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA 2012), January 2012.
31. G. Agosta, A. Barenghi, A. Parata, and G. Pelosi, Automated Security Analysis of Dynamic Web Applications through Symbolic Code Execution. In Proceedings of The 9th International Conference on Information Technology: New Generations (ITNG 2012), Las Vegas, Nevada, USA, April 16-18, 2012. IEEE Computer Society.
32. G. Agosta, A. Barenghi, G. Pelosi. A Code Morphing Methodology to Automate Power Analysis Countermeasures. In 49th Annual ACM/IEEE Design Automation Conference (DAC'12), June 2012.
33. G. Agosta, G. Pelosi, E. Speziale. On Task Assignment in Data Intensive Scalable Computing. In Proceedings of 17th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2013), Lecture Notes in Computer Science, Springer.
34. G. Agosta, A. Barenghi, M. Maggi, G. Pelosi. Compiler-based Side Channel Vulnerability Analysis and Optimized Countermeasures Application. In 50th Annual ACM/IEEE Design Automation Conference (DAC'13), June 2013.
35. G. Agosta, A. Barenghi, G. Pelosi, M. Scandale. Enhancing Passive Side-Channel Attack Resilience through Schedulability Analysis of Data-Dependency Graphs. In Proc. of the Intl. Conf. on Network and Systems Security 2013, Lecture Notes in Computer Science Volume 7873, pp 692-698, June 2013.
36. I. Al Khatib, G. Pelosi, G. Agosta, H. Terio. Security Integration in Medical Device Design: Extension of an Automated Bio-Medical Engineering Design Methodology. In Proceedings of the 11th International Conference on Information Technology: New Generations (ITNG), April 2014.
37. G. Agosta, A. Barenghi, G. Pelosi, M. Scandale. A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software. In 51th Annual ACM/IEEE Design Automation Conference (DAC'14), June 2014.
38. G. Agosta, A. Barenghi, G. Pelosi, M. Scandale. Differential Fault Analysis for Block Ciphers: An Automated Conservative Analysis. To appear in Proceedings of the 7th International Conference of Security of Information and Networks (SIN'14), September 2014 (Best Paper Award).
39. G. Agosta, A. Barenghi, and G. Pelosi. Securing Software Cryptographic Primitives for Embedded Systems against Side Channel Attacks. In Proceedings of the 48^th Annual IEEE International Carnahan Conference on Security Technology, October 2014.
40. G. Agosta, A. Barenghi, G. Pelosi, M. Scandale. Towards Transparently Tackling Functionality and Performance Issues Across Different OpenCL Platforms. In proceedings of the Second International Symposium on Computing and Networking — Across Practical Development and Theoretical Research (CANDAR 2014), December 2014
41. G. Agosta, A. Barenghi, G. Pelosi, M. Scandale. Information leakage chaff: feeding red herrings to side channel attackers. In 52nd ACM/IEEE Design Automation Conference (DAC'15), June 2015
42. G. Agosta, A. Antonini, A. Barenghi, D. Galeri and G. Pelosi. Cyber-Security Analysis and Evaluation for Smart Home Management Solutions. In proceedings of the 49th Annual IEEE International Carnahan Conference of Security Technologies (ICCST 2015), Taipei (Taiwan), September 2015
43. M. Gautschi, M. Scandale, A. Traber, A. Pullini, A. Di Federico, M. Beretta, G. Agosta and L. Benini. Tailoring Instruction-Set Extensions for an Ultra-Low Power Tightly-Coupled Cluster of OpenRISC Cores. In Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) October 5-7, 2015, Daejeon, Korea.
44. S. Cherubin, M. Scandale, G. Agosta. Stack Size Estimation on Machine-Independent Intermediate Code for OpenCL Kernels. In Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 5th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2016), January 18, 2016, Prague, Czech Republic.
45. C. Silvano, G. Agosta, A. Bartolini, A. Beccari, L. Benini, J. Bispo, R. Cmar, J.M.P. Cardoso, C. Cavazzoni, J. Martinovič, G. Palermo, M. Palkovič, P. Pinto, E. Rohou, N. Sanna, K. Slaninová. AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems: the ANTAREX Approach. In Proceedings of Design, Automation, and Test in Europe (DATE 2016), March 2016, Dresden, Germany.
46. J. Flich, G. Agosta, P. Ampletzer, D. Atienza Alonso, C. Brandolese, A. Cilardo, W. Fornaciari, Y. Hoornenborg, M. Kovač, B. Maitre, G. Massari, H. Mlinaric, E. Papastefanakis, F. Roudet, R. Tornero, D. Zoni. Enabling HPC for QoS-sensitive applications: the MANGO approach. In Proceedings of Design, Automation, and Test in Europe (DATE 2016), March 2016, Dresden, Germany.
47. G. Agosta, A. Barenghi and G. Pelosi. Automated Instantiation of Side-Channel Attacks Countermeasures for Software Cipher Implementations. In Proceedings of 1st International Workshop on Malicious Software and Hardware in the Internet of Things (MAL-IoT 2016), Como (Italy), May 2016 (preprint).
48. A. Di Federico and G. Agosta. 2016. A jump-target identification method for multi-architecture static binary translation. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES '16). ACM, New York, NY, USA, , Article 17 , 10 pages. DOI: https://doi.org/10.1145/2968455.2968514
49. G. Agosta, A. Barenghi, G. Pelosi and M. Scandale. Encasing block ciphers to foil key recovery attempts via side channel. In Proceedings of the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, June 2016, pp. 1-8. doi: 10.1145/2966986.2967033 (preprint)
50. G. Agosta, A. Barenghi, C. Brandolese, W. Fornaciari, G. Pelosi, S. Delucchi, M. Massa, M. Mongelli, E. Ferrari, L. Napoletani, L. Bozzi, C. Tieri, D. Cassioli and L. Pomante. “V2I Cooperation for Traffic Management with SafeCOP”. In Proceedings of Euromicro DSD, ASAIT special session, Limassol, Cyprus, August-September 2016. DOI preprint
51. A. Di Federico, M. Payer, and G. Agosta. rev.ng: a unified binary analysis framework to recover CFGs and function boundaries. In Proceedings of the 26th International Conference on Compiler Construction (CC 2017), pages 131-141, February 2017. DOI: https://doi.org/10.1145/3033019.3033028
52. S. Cherubin, G. Agosta, I. Lasri, E. Rohou, and O. Sentieys. Implications of Reduced-Precision Computation in HPC: Performance, Energy and Error. In Proceedings of International Conference on Parallel Computing (ParCo), September 2017.
53. A. Pupykina and G. Agosta. Optimizing Memory Management in Deeply Heterogeneous HPC Accelerators. In Proceedings of the 46th International Conference on Parallel Processing Workshops, August 2017.
54. G. Agosta, W. Fornaciari, G. Massari, A. Pupykina, F. Reghenzani, and M. Zanella. Managing Heterogeneous Resources in HPC Systems. In Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Manage- ment Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, pages 7–12. ACM, 2018.
55. D. Cattaneo, A. Di Bello, S. Cherubin, F. Terraneo, and G. Agosta. Embedded Operating System Optimization through Floating to Fixed Point Compiler Transformation. In Proceedings of the 2018 Euromicro Conference on Digital Systems Design, pages 172–176, 2018.
56. S. Cherubin, G. Agosta, I. Lasri, E. Rohou, and O. Sentieys. Implications of Reduced-Precision Computations in HPC: Performance, Energy and Error. In Advances in Parallel Computing, volume 32, pages 297–306, 2018.
57. R. Nobre, L. Reis, J. Bispo, T. Carvalho, J.M.P. Cardoso, S. Cherubin, and G. Agosta. Aspect-driven mixed-precision tuning targeting gpus. In Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, pages 26–31. ACM, 2018.
58. G. Agosta, E. Baldino, F. Casella, S. Cherubin, A. Leva, and F. Terraneo. Towards a high-performance modelica compiler. In Proceedings of the 13th International Modelica Conference, Regensburg, Germany, March 4–6, 2019, number 157. Linköping University Electronic Press, 2019.
59. M. Festa, N. Gervasoni, S. Cherubin, and G. Agosta. Continuous program optimization via advanced dynamic compilation techniques. In Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, page 2. ACM, 2019.
60. C. Silvano, G. Agosta, A. Bartolini, A. R Beccari, L. Benini, L. Besnard, J. Bispo, R. Cmar, J.M.P. Cardoso, C. Cavazzoni, et al. Supporting the scale-up of high performance application to pre-exascale systems: The ANTAREX approach. In 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pages 116–123. IEEE, 2019.

1. G. Agosta (ed.) et al. Lessons learnt from 2PARMA project. 2PaRMA deliverable D7.1.2, March 2013
2. G. Agosta (ed.), F. Castro, A. Di Biagio and V. Zaccaria. Specification of Computing Fabric-specific extensions to OpenCL. 2PaRMA deliverable D2.1.1, January 2011.
3. G. Agosta (ed.). Split Compilation Tools (static and dynamic compilers) Specification. OMP Report D2.2, January 2009.
4. S. Campanoni, G. Agosta, and S. Crespi Reghizzi. A parallel dynamic compiler for CIL bytecode. SIGPLAN Not. 43, 4 (Apr. 2008), 11-20. (pdf)
5. S. Campanoni, G. Agosta, S. Crespi Reghizzi. A parallel dynamic compiler for CIL bytecode. Internal Report no. 2008.3, Politecnico di Milano, Dipartimento di Elettronica e Informazione, January 2008.
6. G. Agosta, G. Pelosi. Countermeasures for the Simple Branch Prediction Analysis. Cryptology ePrint Archive report 2006/482, December 2006.
7. F. Bruschi, G. Agosta, D. Sciuto, G. Ferrara, N. Bannow, P. Kajfasz. Requirements on Metrics for the Early Communication Cost Estimation. ICODES Report D1, February 2005.
8. G. Agosta. Dynamic Compilation for Architectures with Instruction-Level Parallelism. Doctoral dissertation, Politecnico di Milano, March 2004.
9. G. Agosta. System C Specifications for Hardware/Software Partitioning. Internal Report no. 2002.6, Politecnico di Milano, Dipartimento di Elettronica e Informazione, January 2002.
10. G. Agosta. Tecniche avanzate di compilazione applicate a macchine parallele e riconfigurabili. Tesi di Laurea, Politecnico di Milano, April 2000.

1. J. Flich, G. Agosta, P. Ampletzer, D. Atienza Alonso, C. Brandolese, E. Cappe, A. Cilardo, L. Dragić, A. Dray, A. Duspara, W. Fornaciari, G. Guillaume, Y. Hoornenborg, A. Iranfar, M. Kovač, S. Libutti, B. Maitre, J. M. Martínez, G. Massari, H. Mlinarić, E. Papastefanakis, T. Picornell, I. Piljić, A. Pupykina, F. Reghenzani, I. Staub, R. Tornero, M. Zapater, D. Zoni. MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. In Proceedings of Euromicro Conference on Digital System Design (DSD), August 2017.
2. C. Silvano, A. Bartolini, A. Beccari, C. Manelfi, C. Cavazzoni, D. Gadioli, E. Rohou, G. Palermo, G. Agosta, J. Martinovič, J. Bispo, J. MP Cardoso, J. Barbosa, K. Slaninová, L. Benini, M. Palkovič, N. Sanna, P. Pinto, R. Cmar, R. Nobre, S. Cherubin. The ANTAREX Tool Flow for Monitoring and Autotuning Energy Efficient HPC Systems. In Proceedings of the SAMOS 2017 - International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation, Samos (Greece), July 2017.
3. C. Silvano, G. Agosta, S. Cherubin, D. Gadioli, G. Palermo, A. Bartolini, L. Benini, J. Martinovic, M. Palkovic, K. Slaninova
, J. Bispo, J. M. P. Cardoso, R. Abreu, P. Pinto, C. Cavazzoni, N. Sanna, A. R. Beccari, R. Cmar, and E. Rohou. The ANTAREX Approach to Autotuning and Adaptivity for Energy Efficient HPC Systems. In Proceedings of the Special Session on Funded Projects at Computing Frontiers 2016, Como (Italy), May 2016.
4. C. Silvano, G. Agosta, A. Bartolini, A. Beccari, L. Benini, J. M. P. Cardoso, C. Cavazzoni, R. Cmar, J. Martinovic, G. Palermo, M. Palkovic, E. Rohou, N. Sanna, and K. Slaninova
. ANTAREX - AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems. In proceedings of 18th IEEE Conference on Computational Science and Engineering, Special Session on FET-HPC and Exascale Recently EU-Funded Projects, Porto (Portugal), October 2015.
5. J. Flich, G. Agosta, P. Ampletzer, D. Atienza Alonso,
 A. Cilardo, W. Fornaciari, M. Kovac, F. Roudet, and D. Zoni
. The MANGO FET-HPC Project: An Overview. In proceedings of 18th IEEE Conference on Computational Science and Engineering, Special Session on FET-HPC and Exascale Recently EU-Funded Projects, Porto (Portugal), October 2015.
6. A. Agneessens, F. Buemi, S. Delucchi, M. Massa, G. Agosta, A. Barenghi, C. Brandolese, W. Fornaciari, G. Pelosi, D. Cassioli, L. Pomante, L. Napoletani, L. Bozzi, E. Ferrari, C. Tieri, M. Mongelli. “Safe Cooperative CPS: A V2I Traffic Management scenario in the SafeCOP project”. In Proceedings of the SAMOS XVI Conference, Agios Konstantinos, Greece, July 2016. preprint
7. G. Agosta, C. Brandolese, F. Clasadonte, W. Fornaciari, F. Garzotto, M. Gelsomini, M. Grotto, C. Fra', D. Noferi and M. Valla. Playful Supervised Smart Spaces (P3S): A framework for designing, implementing and deploying multisensory play experiences for children with special needs. In proceedings of 2015 EUROMICRO Digital System Design Conference, Funchal (Portugal), August 2015.
8. D. Gadioli, S. Libutti, G. Massari, E. Paone, M. Scandale, P. Bellasi, G. Palermo, V. Zaccaria, G. Agosta, W. Fornaciari, and C. Silvano. OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms. In 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), August 2014.
9. G. Massari, E. Paone, M. Scandale, P. Bellasi, G. Palermo, V. Zaccaria, G. Agosta, W. Fornaciari, C. Silvano. Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures. In Proceedings of the 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, LNCS, Springer, April 2014.
10. C. Silvano, W. Fornaciari, S. Crespi-Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. M. Zins, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, I. Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, J. Ansari, P. Mähönen, B. Vanthournout: Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach. ReCoSoC 2011.
11. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI 2010), July 2010, Kefalonia, Greece.

1. G. Agosta. “The MANGO FET-HPC Project: An Overview”, held at 18th IEEE Conference on Computational Science and Engineering, Special Session on FET-HPC and Exascale Recently EU-Funded Projects, Porto (Portugal), October 2015.
2. G. Agosta and M. Scandale, “The 2PARMA OpenCL Compiler Toolchain”, held at the Fall School on Programming Paradigms for Multicore Embedded Systems, Oct 2012, Freudenstadt, Germany.
3. G. Agosta, “Application Virtualization: The 2PARMA Approach”, held at HiPEAC Virtualization Cluster Meeting, October 2010, Barcelona, Spain.
4. G. Agosta, “The 2PARMA Compiler Toolchain”, held at HiPEAC Compilation Cluster Meeting, October 2010, Barcelona, Spain.

• HiPEAC Paper Award 2015 for the paper “Information leakage chaff: feeding red herrings to side channel attackers”.
• Best Paper Award (Overall & Cryptographic Techniques) at SIN 2014 for the paper “Differential Fault Analysis for Block Ciphers: an Automated Conservative Analysis”
• HiPEAC Paper Award 2014 for the paper “A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software”.
• HiPEAC Paper Award 2013 for the paper “Compiler-based side channel vulnerability analysis and optimized countermeasures application”.
• HiPEAC Paper Award 2012 for the paper “A code morphing methodology to automate power analysis countermeasures”.
• Best Paper Award (Applications area) at ACM SAC 2008 for the paper “Dynamic Configuration of Application-Specific Implicit Instructions for Embedded Pipelined Processors”

Researcher with tenure/Assistant Professor (Ricercatore Confermato) at Politecnico di Milano. I currently teach the following courses:

• Code Optimization and Transformation (compiler construction, 2013-current) with the Laurea Specialistica in Ingegneria Informatica (Computer Engineering, graduate program).
• Energy aware design of computing systems and applications (2014, 2016), with the Dottorato in Ingegneria dell'Informazione (doctoral program in Information Technology), as a co-organizer with Prof. William Fornaciari.

In the past, I used to teach the following courses:

• Algoritmi e Principi dell'Informatica (principles of algorithms and data structures, 2010) within the Laurea in Ingegneria Informatica (Computer Engineering, undergraduate program);
• Piattaforme Software per la Rete (software platforms for networking, 2011-2012) within the Laurea in Ingegneria Informatica and Laurea in Ingegneria delle Telecomunicazioni (Computer Engineering and Telecommunications Engineering, undergraduate programs).
• Informatica 3 (principles of programming language design, algorithms and data structures, 2008-2010) within the Laurea in Ingegneria Informatica (Computer Engineering, undergraduate program);
• Laboratorio Software (software design and operating systems laboratory, 2008-2010) within the Laurea Specialistica in Ingegneria Informatica (Computer Engineering, graduate program).

Junior Researcher (Ricercatore) at Politecnico di Milano. I have taught the following courses during my three years as a Junior Researcher:

• Informatica 3 (principles of programming language design, algorithms and data structures, 2007) within the Laurea in Ingegneria Informatica (Computer Engineering, undergraduate program);
• Laboratorio Software (software design and operating systems laboratory, 2005-2007) within the Laurea Specialistica in Ingegneria Informatica (Computer Engineering, graduate program);
• Informatica C (fundamentals of computer programming and architecture, 2005) within the Laurea in Ingegneria Chimica e dei Materiali (Chemical Engineering, undergraduate program);

Term Researcher (Assegnista di Ricerca) at Politecnico di Milano. During this year, I taught the following course as contract professor:

• Informatica C (fundamentals of computer programming and architecture) within the Laurea in Ingegneria Chimica e dei Materiali (Chemical Engineering, undergraduate program);

Teaching Assistant at Politecnico di Milano and at the Advanced Learning and Research Institute (ALaRI) of Università della Svizzera italiana.

I have taught (and in some cases still teach) in the following courses:

• Fondamenti di Informatica (Foundations of computer programming) at Politecnico di Milano, within the undergraduate programs in Mathematical Engineering (2013-current). I manage C language programming laboratories in this course.
• Fondamenti di Informatica (Foundations of computer programming) at Politecnico di Milano, within the undergraduate programs in Telecommunication Engineering (2013-2014) and Computer Engineering (2015-current). I teach C programming in this course, and Python since 2015.
• Advanced Computer Architecture (2013-current) and High Performance Processors at Politecnico di Milano, within the Master of Science in Electrical Engineering and Computer Science program in coordination with University of Illinois at Chicago (2002-2006). I act as teaching assistant on VLIW architectures, as well as on other topics in computer architectures, such as performance evaluation, pipelining, and GPGPU architectures.
• Traduzione e Ottimizzazione del Codice (code translation and optimization) at Politecnico di Milano, within the Laurea in Ingegneria Informatica (Computer Engineering) program (2007).
• Software Compilers at ALaRI, within the Master in Embedded Systems Engineering (2003-2012). I acted as laboratory assistant, additional lecturer and tutor on back-end and intermediate representation in compilers.
• Linguaggi e Traduttori, Linguaggi formali e compilatori (Formal languages and compilers), Analisi e Ottimizzazione dei Programmi (Analysis and optimization of programs) at Politecnico di Milano, within the Laurea in Ingegneria Informatica (Computer Engineering) program (2002-2007). I acted as teaching assistant on both parsing techniques and tool (Flex and Bison) and back-end and intermediate representation in compilers, using the SUIF framework.
• Architectures for multimedia systems at Politecnico di Milano at Como, within the Laurea Specialistica in Ingegneria Informatica (Computer Engineering, graduate program, 2005-2006). I acted as teaching assistant on pipelining, VLIW architectures and multiprocessors.
• Algoritmi e Strutture Dati (Algorithms and data structures) at Politecnico di Milano, within the undergraduate program in Mathematical Engineering (2004-2005). I taught Python programming and the foundations of algorithmics.
• Informatica C (Foundations of computer programming) at Politecnico di Milano, within the undergraduate programs in Chemistry and Materials Science (2001-2003). I taught C language programming in this course.

Teaching Assistant in ad hoc course of Software Compilers organized at Politecnico di Milano for STMicroelectronics. The course aimed at providing industry researchers with an overview of modern compiler technology.

Teacher in industry-oriented courses of computer programming (C/C++), organized by Qgroup. The courses aimed at providing new employees with sound programming skills for embedded software implementation.

I have been active in research activities funded by the European Commission in the Framework Programmes 6 and 7, as well as in Horizon 2020.

Starting in Q4 2015, I am involved in the ANTAREX (Task leader for compiler technology) and MANGO (deputy representative for Politecnico di Milano to the General Assembly and Work Package leader for the software stack) EU H2020 FET-HPC projects.

Starting in Q1 2016, I am involved in the M2DC EU H2020 LEIT project. Starting in Q2 2016, I'll be involved in the ECSEL SafeCOP project.

In 2015, I have been task leader for the development of Smart Objects in the EIT ICT Lab activity P3S Playful Supervised Smart Spaces.

I led (2010-2013) Workpackage 2 on compiler technologies and programming models in the 2PARMA EU FP7 project (deemed a success story by the European Commission), where Politecnico di Milano was the coordinating partner. I was also Workpackage 3 leader in the Artemis SMECY project, during the same timeframe.

Collaboration to the EU FP7 project OpenMediaPlatform. In OpenMediaPlatform, I was deputy representative of Politecnico di Milano (coordinating partner for the second half of the project) in the General Assembly.

Collaboration to the EU FP6 project ICODES. Within ICODES, I worked on the definition of metrics for communication cost assessment in early phases of system design.

In addition to the professional and research activities, I also take part in a range of service activities.

I was Local arrangement co-chair for the 2008 MICRO conference. I have been a member of the program committee (and session/organization chair) of the 2PARMA workshop (associated with ARCS 2010) and the DEPCP Friday Workshop (associated with DATE 2010).

I have been general co-chair for the 2011 and 2012 PARMA workshop (associated with the ARCS conference) and DEPCP 2011 Friday Workshop (associated with DATE 2011), as well as finance chair for ARCS2011. I have been general co-chair for the 2013 PARMA Workshop, associated with the HiPEAC 2013 conference and sponsored by Nvidia. I am/have been general co-chair of PARMA-DITAM Workshop 2015-2017 and CS2 Workshop (2014-2018), associated with the HiPEAC Conference.

I have served in the technical program committee of:

• HIP3ES 2016-2018 International Workshop on High Performance Energy Efficient Embedded Systems (4th Edition)
• DSD 2015-2018 Special Session on Architecture and Hardware for Security Applications
• SAMOS 2015-2016
• HIPCS 2015's International Workshop on Architecture-Aware Simulation and Computing
• NTMS 2108 IFIP International Conference on New Technologies, Mobility & Security

Subreferee for several conferences, among which, in 2010, the MICRO conference, the International Conference on Compiler Construction (CC), Design and Test in Europe (DATE), Design Automation Conference (DAC), International Conference on Embedded Computing Systems: Architectures, Modeling and Simulation (SAMOS), and the IEEE Symposium on Application Specific Processors (SASP). I've also provided peer reviews for several journals, including the IEEE Transactions on Computers and Journal of Systems Architecture, published by Elsevier.

I've been co-advisor for two doctoral students (Andrea Di Biagio, Ettore Speziale) and advisor for one doctoral student (Michele Scandale). I'm currently advisor for three doctoral students (Alessandro Di Federico, Stefano Cherubin, Anna Pupykina).

I've been advisor or co-advisor for 10+ master's theses at Politecnico di Milano and one at ALaRI, as well as several bachelor's theses at Politecnico di Milano.

I've been controrelatore (external examiner) for a PhD dissertation (Alberto Gallini, University of Milan-Bicocca, 2007) and several master's theses at Politecnico di Milano and Universita' degli Studi di Bergamo.

I'm part of the Ph.D. committee (as external examiner) of Pedro Pinto at Universidade do Porto (Portugal).

I am currently serving on the logistics board of the School of Industrial & Information Engineering (Ingegneria Industriale e dell'Informazione) at Politecnico di Milano.

I have been the PhD students representative at the Department council in 2001-2002.

I am currently working mostly using the Python and C languages, and I have taught both in undergraduate courses. I am also proficient with several compiler construction tools, including Lex/Flex, Yacc/Bison, SUIF, as well as with the popular HW/SW design language, SystemC.