I am interested in computer architectures, from pipeline structure to design methodologies for embedded systems.
We work on the design of advanced pipeline architecture for hiding latencies and speeding up computation by means of pipeline reconfiguration.
The exploration of the architectural design space in terms of both energy and performance is of mainly importance for a broad range of embedded platforms based on the System-On-Chip approach. We propose a methodology for the co-exploration of the design space composed of architectural parameters and source program transformations.
This project aims at analyzing the application of source code transformations to superscalar parameterized architectures. Currently, a Pareto Simulated Annealing (PSA) heuristic technique is being used to span the multi-objective co-design space composed of the product of the parameters related to the selected program transformations and the configurable architecture of the memory subsystem.