\part{Assembler}
\label{cha:ASSEMBLER}

\begin{slide}{Assembler workflow}
\begin{itemize}
   \item Initialize internal data structures
   \item Check input code for syntactic errors
	 \item Translate labels to memory addresses
	 \item Translate assembly instruction to machine code
   \item Write out the object file
\end{itemize}
\end{slide}


\begin{slide}{Assembly format}
\begin{itemize}
  \item An instruction specifies an operation type and a list of operands.
	\item Operand types:
		\begin{itemize}
  		 \item register identifiers
  		 \item immediate values
  		 \item address values
		\end{itemize}
	\item In ternary instructions the destination register and the second source register can be indirectly addressed.
\end{itemize}
\end{slide}


\begin{slide}{Assembly format: Notation}
\begin{itemize}
   \item \texttt{Rn} Register `n'
   \item \texttt{Rdest} Destination Register
   \item \texttt{Rsource1} First source operand
   \item \texttt{Rsource2} Second source operand
   \item \texttt{(Rn)} Indirect register `n'
   \item \texttt{\#imm} Immediate value, where \texttt{imm} is an integer value.
\end{itemize}
\end{slide}


\begin{slide}{Instructions and Directives}
\begin{itemize}
	\item Assembler directives use a subset of the \texttt{GNU assembler directives}
	\item Instructions come in four formats:
		\begin{itemize}
  		 \item Ternary instructions
  		 \item Binary instructions
  		 \item Unary instructions
			 \item Branch instructions
		\end{itemize}
\end{itemize}
\end{slide}

\begin{slide}{Object file format}
\centering
\resizebox{0.5\textwidth}{!}{\includegraphics{asm/objectfileformat}}

Header: ``LFCM'' plus 16 reserved bytes
\end{slide}


\begin{slide}{Ternary Instructions: Arithmetics}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ADD}               &\emph{Add binary} \\

   \hline

   Syntax:           &ADD Rdest RSource1 RSource2 \\
   Examples           &Semantics \\
    ADD R2 R1 R3      &R2 $\leftarrow$ R1 + R3 \\
    ADD R2 R1 (R3)    &R2 $\leftarrow$ R1 + [R3] \\
    ADD (R2) R1 (R3)  &[R2] $\leftarrow$ R1 + [R3] \\
   &\\
\end{tabular}
Arithmetic Instructions: ADD, SUB, MUL, DIV
\end{slide}


\begin{slide}{Ternary Instructions: Logic \& Bitwise}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ANDL}              &\emph{AND logical} \\
   
   \hline
   
   Syntax:            &ANDL Rdest RSource1 RSource2 \\
   Examples            &Semantics \\
    ANDL R2 R1 R3      &R2 $\leftarrow$ R1 \&\& R3 \\
    ANDL R2 R1 (R3)    &R2 $\leftarrow$ R1 \&\& [R3] \\
    ANDL (R2) R1 (R3)  &[R2] $\leftarrow$ R1 \&\& [R3] \\
   &\\
\end{tabular}
\begin{description}
\item[Logical] ANDL, ORL, EORL
\item[Bitwise] ANDB, ORB, EORB
\end{description}
\end{slide}


\begin{slide}{Ternary Instructions: Shift \& Rotate}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SHR}               &\emph{Binary Shift to Right} \\
   \hline

   Syntax:           &SHR Rdest RSource1 RSource2 \\
      Examples            &Semantics \\
    SHR R2 R1 R3      &R2 $\leftarrow$ R1 $\gg$ R3 \\
    SHR R2 R1 (R3)    &R2 $\leftarrow$ R1 $\gg$ [R3] \\
    SHR (R2) R1 (R3)  &[R2] $\leftarrow$ R1 $\gg$ [R3] \\
   &\\
\end{tabular}
\begin{description}
\item[Shift] SHR, SHL
\item[Rotate] ROTR, ROTL
\end{description}
\end{slide}


\begin{slide}{Ternary Instructions: NEG}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{NEG}            &\emph{Negate} \\
   \hline

   Syntax:           &NEG Rdest RSource1 RSource2 \\
      Examples            &Semantics \\
    NEG R2 R1 R3     &R2 $\leftarrow$ - R3 \\
    NEG R2 R1 (R3)   &R2 $\leftarrow$ - [R3] \\
    NEG (R2) R1 (R3) &[R2] $\leftarrow$ - [R3] \\

   Note:             &RSource1 is unused. \\
\end{tabular}
\end{slide}


\begin{slide}{Binary Instructions: Arithmetics}
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{ADDI}               &\emph{Add with Immediate operand} \\

   \hline
   
   Syntax:           &ADDI Rdest RSource1 \#Immediate \\
   Example          &Semantics \\
    ADDI R2 R1 \#VAL     &R2 $\leftarrow$ R1 + VAL \\
   &\\
\end{tabular}
Arithmetic Instructions: ADDI, SUBI, MULI, DIVI
\end{slide}

\begin{slide}{Binary Instructions: Logic \& Bitwise}
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{ANDLI}              &\emph{AND with Immediate operand}\\
   
   \hline
   
   Syntax:            &ANDLI Rdest RSource1 \#Immediate \\
   Example          &Semantics \\
    ANDLI R2 R1 \#VAL     &R2 $\leftarrow$ R1 \&\& VAL \\
   &\\
\end{tabular}
\begin{description}
\item[Logical] ANDL, ORL, EORL
\item[Bitwise] ANDB, ORB, EORB
\end{description}
\end{slide}


\begin{slide}{Binary Instructions: Shift \& Rotate}
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{SHRI}               &\emph{Binary Shift to Right} \\
   \hline

   Syntax:           &SHRI Rdest RSource1 \#Immediate \\
   Example          &Semantics \\
    SHRI R2 R1 \#VAL     &R2 $\leftarrow$ R1 $\gg$ VAL \\
   &\\
\end{tabular}
\begin{description}
\item[Shift] SHRI, SHLI
\item[Rotate] ROTRI, ROTLI
\end{description}
\end{slide}


\begin{slide}{Binary Instructions: NOTL and NOTB}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{NOTL}            &\emph{Logical complement} \\
   \hline

   Syntax:           &NOT Rdest RSource1 \#Immediate \\
   Example:          &Semantics \\
    NOTL R2 R1 \#VAL     &R2 $\leftarrow$ ! R1\\
   Note:             &VAL is unused. \\
	 &\\
\end{tabular}
}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{NOTB}            &\emph{Binary complement} \\
   \hline

   Syntax:           &NOTB Rdest RSource1 \#Immediate \\
   Example          &Semantics \\
    NOTB R2 R1 \#VAL     &R2 $\leftarrow$ $\sim$ R1\\
\end{tabular}
}\end{slide}


\begin{slide}{Unary Instructions: NOP, HALT and MOVA}
\begin{tabular}{lp{0.6\textwidth}}
   \textbf{NOP}            &\emph{No Operation} \\
   Syntax:           &NOP \\

   \hline
   \textbf{HALT}            &\emph{Halt the machine processor} \\

   \hline
   \textbf{MOVA}            &\emph{Move Address to Register Location} \\

   Syntax:           &MOVA RDest Address \\
   Example          &Semantics \\
    MOVA R2 L1     &R2 $\leftarrow$ L1 (where L1 is a Label) \\
\end{tabular}
\end{slide}


\begin{slide}{Binary Instructions: LOAD and STORE}
\begin{tabular}{lp{0.65\textwidth}}
   \textbf{LOAD}            &\emph{Fill a register with a value read from memory} \\
   Syntax:           &LOAD RDest Address \\
   Example          &Semantics \\
    LOAD R2 L1     &R2 $\leftarrow$ [L1] (where L1 is a Label) \\

   \hline

   \textbf{STORE}            &\emph{Spill a value} \\
   Syntax:           &STORE RSource Address \\
   Example          &Semantics \\
    STORE R2 L1     &L1 $\leftarrow$ R2 (where L1 is a Label) \\
\end{tabular}
\end{slide}



\begin{slide}{Binary Instructions: SEQ, SGE, etc.}
\begin{tabular}{lp{0.65\textwidth}}
   \textbf{Scc}            &\emph{Set according to condition `cc'} \\
   \hline
   Syntax:           &Scc Rdest Address \\
   Semantics:        &IF cc == 1 THEN Rdest $\leftarrow$ 1;
                     ELSE Rdest $\leftarrow$ 0. \\
   Note: &\texttt{Address} parameter is unused.
\end{tabular}

\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{1.4\textwidth}}
   Possible values for `cc':    &\\
   \textbf{EQ}               &set on equal; \\
   \textbf{GE}               &set on greater than or equal; \\
   \textbf{GT}               &set on greater than; \\
   \textbf{LE}               &set on less than or equal; \\
   \textbf{LT}               &set on less than; \\
   \textbf{NE}               &set on not equal; \\

   Description:      & `cc' is tested: if the condition is true, `Rdest'
                      is set to one, otherwise to zero. \\
   Example:
      SGT R2 0       & Set the value of R2 to 1 if the condition GT is verified; 0 otherwise. \\
\end{tabular}
}\end{slide}


\begin{slide}{Binary Instructions: READ and WRITE}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.9\textwidth}}
   \textbf{READ}            &\emph{Read from standard input an integer value} \\
   \hline

   Syntax:           &READ RSource Address \\
   Example          &Semantics \\
    READ R2 0      &Read from input an 32-bit signed integer value, and store the value to `R2'. \\
   Note:             &\texttt{Address} parameter is unused. \\
\end{tabular}
}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.9\textwidth}}
   \textbf{WRITE}            &\emph{Write to standard output an integer value} \\
   \hline

   Syntax:           &WRITE RSource Address \\
   Example          &Semantics \\
    WRITE R2 0        &Write to standard output a 32-bit signed integer value stored into R2. \\
   Note:             &\texttt{Address} parameter is unused. \\
\end{tabular}
}\end{slide}


\begin{slide}{Jump Instructions}
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{Bcc}            &\emph{Branch on condition cc} \\
   \hline

   Syntax:           &Bcc Label \\
   Semantics:       &IF cc == 1 THEN \\
                                 & jump to label \texttt{Label}. \\
   Description:      & `cc' is tested: if the condition is true,
                      the PC is set to the label address. \\
   Examples:    &\\
   BEQ L1 &Branch to L1 on ``equal to zero''\\
   BT L3 &Always branch to L3\\
   BLT L2 &Branch to L2 on ``less than zero''\\
\end{tabular}
\end{slide}


\begin{slide}{Condition Codes (1)}
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{EQ}  &Branch on equal; \\
   \textbf{GE}  &Branch on greater than or equal; \\
   \textbf{T}   &Branch always; \\
   \textbf{F}   &Never branch; \\
   \textbf{HI}  &Branch on higher than \\
   \textbf{LS}  &Branch on lower than or same; \\
   \textbf{GT}  &Branch on greater than; \\
   \textbf{LE}  &Branch on less than or equal; \\
\end{tabular}
\end{slide}

\begin{slide}{Condition Codes (2)}
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{LT}  &Branch on less than; \\
   \textbf{NE}  &Branch on not equal; \\
   \textbf{CC}  &Branch on carry clear; \\
   \textbf{CS}  &Branch on carry set; \\
   \textbf{VC}  &Branch on overflow clear; \\
   \textbf{VS}  &Branch on overflow set; \\
   \textbf{BPL} &Branch on plus (i.e. positive);\\
   \textbf{BMI} &Branch on minus (i.e. negative);\\
\end{tabular}
\end{slide}


\begin{slide}{Assembler Directives}
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{.data}    &Beginning of a block of data directives \\
   \textbf{.text}    &Beginning of a block of instructions \\
   \textbf{.word}    &Reserve and set a memory word (32-bit) in the data segment \\
   \textbf{.space}   &Reserve a given number of bytes into the data segment \\
\end{tabular}
\end{slide}

\begin{slide}{Assembler Directives: \textbf{.word}}
\emph{Reserve and set a memory word (32-bit) in the data segment}
\begin{tabular}{lp{0.7\textwidth}}
   Syntax:           &\texttt{.word} VAL \\
   Semantics:       &Reserve a 32-bit memory location inside the data segment and set the starting
                     value of the location to \texttt{VAL} \\
   Examples: &\\
      \texttt{.word 5} &reserve a word, set its content to 5\\
      \texttt{.word 0} &reserve a word, set its content to 0\\
\end{tabular}
\end{slide}

\begin{slide}{Assembler Directives: \textbf{.space}}
\emph{Reserve (but not initialize) a given number of bytes into the data segment} 
\begin{tabular}{lp{0.7\textwidth}}
   Syntax:           &\texttt{.space} VAL \\
   Semantics:       &Reserve \texttt{VAL} (contiguous) bytes inside the data segment. \\
   Examples: &\\
      \texttt{.space 8}     &5 contiguous bytes reserved \\
      \texttt{.space 32}    &32 contiguous bytes reserved \\
\end{tabular}
\end{slide}
