\part{MACE}
\label{cha:MACE}

\begin{slide}{MACE Architecture}
\centering
\resizebox{0.8\textwidth}{!}{\includegraphics{mace/architecture}}
\end{slide}


\begin{slide}{MACE Bootstrap}
\begin{itemize}
   \item Test if the object file exists and is readable
   \item Set machine registers (including \texttt{PC}) to zero
   \item Resere a 2Kb block of memory (code and data segments)
   \item Load machine code from object file to code segment
   \item Load data from object file to data segment
\end{itemize}
\end{slide}

\begin{slide}{MACE Execution Loop}
\begin{itemize}
   \item Repeat:
   \begin{itemize}
      \item fetch the next instruction according to \texttt{PC}
      \item decode the fetched instruction
      \item execute the instruction
      \item update the content of the register file
      \item update the value of \texttt{PC}
      \item update the value of \texttt{PSW}
   \end{itemize}
   \item Until an \texttt{HALT} instruction is encountered.
\end{itemize}
\end{slide}


\begin{slide}{MACE Register File}
\begin{itemize}
   \item 32 General-Purpose 32-Bit registers: \texttt{R0} - \texttt{R31}
		\begin{itemize}
			\item Note that \texttt{R0} is wired to 0!
		\end{itemize}
   \item 32-Bit Program Counter (\texttt{PC})
   \item 32-Bit Status Register (\texttt{PSW})
\end{itemize}
\end{slide}


\begin{slide}{MACE Processor Status Word}
\resizebox{10cm}{!}{\includegraphics{mace/psw}}
\scriptsize
\begin{itemize}
  \item N (Negative): set if the most significant bit of the result of an instruction is set to 1; cleared otherwise.
	\item Z (Zero): set if the result of an instruction  is equal to zero; cleared otherwise.
	\item V (Overflow): set only if an arithmetic overflow occurs implying that the result cannot be represented in the operand size.
	\item C (Carry): set if a carry out of the most significant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction.
\end{itemize}
\end{slide}

\begin{slide}{MACE Instruction Format}
\centering
\resizebox{9cm}{!}{\includegraphics{mace/instructions}}
\end{slide}


\begin{slide}{MACE Instruction Format}
\begin{tabular}{cl}
\begin{minipage}{5cm}
\resizebox{4.5cm}{!}{\includegraphics{mace/fun_bits}} 
\end{minipage} & %
\begin{minipage}{5.5cm}
\resizebox{4.5cm}{!}{
\begin{tabular}{p{1\textwidth}}
If CARRY is set, the result of the binary operation is incremented by the carry bit of the PSW\\
If SIGN is set, RSOURCE1 and RSOURCE2 are treated as signed integers\\
INDIRECT\_RDEST is set to 1 if the destination register is indirectly addressed\\
INDIRECT\_RSOURCE2 is set to 1 if the `RSOURCE2' register is indirectly addressed\\
\end{tabular}
}\end{minipage}\\
\end{tabular}
\end{slide}

\begin{slide}{Example: ADD}
\centering
\resizebox{8cm}{!}{\includegraphics{mace/exampleADD}}
\end{slide}


\begin{slide}{Instruction Set: Notation}
Possible effects on \texttt{PSW} bits:
\begin{itemize}
   \item \texttt{U} The state of the bit is undefined
   \item \texttt{-} The bit remains unchanged 
   \item \texttt{*} The bit is set or cleared according to the outcome of the instruction
\end{itemize}

Operands:
\begin{itemize}
   \item \texttt{Rn} Register location \emph{n}
   \item \texttt{imm} Immediate value (16 bit or 32 bits)
\end{itemize}
\end{slide}


\begin{slide}{Instruction Set: ADD}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{ADD}               &\emph{Add binary} \\

   \hline
   
   Syntax:           &ADD [Rdest] [RSource1] [RSource2] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] + [RSource2] \\
   Binary Opcode:    &`0000'\\
   &\\
   Description:      &Add the source operand `Rsource1' to `Source2' and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  *  *} \\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: ADDI}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{ADDI}               &\emph{Add with Immediate operand} \\

   \hline
   
   Syntax:           &ADDI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] + \#[Immediate] \\
   Binary Opcode:    &`0000'\\
   &\\
   Description:      &Add the source operand `Rsource1' to the `immediate' value and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  *  *} \\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: MOVA}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{MOVA}            &\emph{Move Address to Register Location} \\
   \hline

   Syntax           &MOVA [RDest] [Address] \\
   Semantics:       &[Rdest] $\leftarrow$ [Address] \\
   Binary Opcode:    &`0001'\\
   &\\
   Description:     &Move the value of [Address] into `RDest'. Address is a 20-bit value \\
   Usage:           &MOVA instructions are typically used when we works on address (pointers) or arrays. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: LOAD}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{LOAD}            &\emph{Fill a register with a value read from memory} \\
   \hline

   Syntax           &LOAD [RDest] [Address] \\
   Semantics:       &[Rdest] $\leftarrow$ *[Address] \\
   Binary Opcode:    &`0100'\\
   &\\
   Description:     &Load the value previously stored at `Address' memory location inside the register `Rdest' \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: STORE}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{STORE}            &\emph{Spill a value} \\
   \hline

   Syntax           &STORE [RSource] [Address] \\
   Semantics:       &*[Address] $\leftarrow$ [RSource] \\
   Binary Opcode:    &`0101'\\
   &\\
   Description:     &Store the value of `Rsource' to the `Address' memory location \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: Scc (1)}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{Scc}            &\emph{Set according to condition `cc'} \\
   \hline

   Syntax           &Scc [Rdest] [Address] \\
   Semantics        &IF cc == 1 THEN [Rdest] $\leftarrow$ 1;
                     ELSE [Rdest] $\leftarrow$ 0. \\
                     
   Note:            &Address is unused. \\
\end{tabular}
'cc' is checked against \texttt{PSW} register. 
E.g.: `SEQ Rx' stores 1 into Rx if bit `N' is set in \texttt{PSW}; otherwise Rx is set to zero.
}\end{slide}


\begin{slide}{Instruction Set: Scc (2)}
\begin{tabular}{lp{0.7\textwidth}}
   Binary Op-codes:    &\\
   SEQ               &`0111'\\
   SGE               &`1000'\\
   SGT               &`1001'\\
   SLE               &`1010'\\
   SLT               &`1011'\\
   SNE               &`1100'\\
   &\\
   
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{0   *   0  0} \\
   &\\
\end{tabular}
\end{slide}


\begin{slide}{Instruction Set: READ}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{READ}    &\emph{Read from standard input an integer value} \\
   \hline
   Syntax           &READ [RSource] [Address] \\
   Semantics:       &Read from input an 32-bit signed integer value, and store the value to `RSource'. Address is unused. \\
   Binary Opcode:    &`1101'\\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: Write}
\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.7\textwidth}}
   \textbf{WRITE}            &\emph{Write to standard output an integer value} \\
   \hline

   Syntax           &WRITE [RSource] [Address] \\
   Semantics:       &Write to standard output a 32-bit signed integer value stored into Rsource.
                    Address is unused. \\
   Binary Opcode:    &`1110'\\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}
}\end{slide}


\begin{slide}{Instruction Set: Jump}
%\resizebox{0.9\textwidth}{!}{
\begin{tabular}{lp{0.9\textwidth}}
   \textbf{Bcc}     &\emph{Branch on condition cc} \\
   \hline
   Syntax           &Bcc [Label] \\
   Semantics        &IF cc == 1 THEN \\
                    & [\texttt{PC}] $\leftarrow$ [\texttt{PC}] + \textbf{Displacement}; \\
\end{tabular}

\begin{itemize}
\item \emph{Displacement} is the distance between \emph{\texttt{PC}} and the label address
\item `cc' is checked against the \texttt{PSW} register
\item E.g.: `BEQ Label' performs a branch to `label' address if bit N is set in \texttt{PSW}. Otherwise Rx is set to zero.
\end{itemize}
\end{slide}


\begin{slide}{Instruction Set: Branch Conditions}
\resizebox{0.7\textwidth}{!}{
\begin{tabular}{lllll}
   BT             &`0000' & $\phantom{5}$ &  BVC            &`1000' \\
   BF             &`0001' &	$\phantom{5}$ &  BVS            &`1001' \\
   BHI            &`0010' &	$\phantom{5}$ &  BPL            &`1010' \\
   BLS            &`0011' &	$\phantom{5}$ &  BMI            &`1011' \\
   BCC            &`0100' &	$\phantom{5}$ &  BGE            &`1100' \\
   BCS            &`0101' &	$\phantom{5}$ &  BLT            &`1101' \\
   BNE            &`0110' &	$\phantom{5}$ &  BGT            &`1110' \\
   BEQ            &`0111' &	$\phantom{5}$ &  BLE            &`1111' \\
\end{tabular}  
}\end{slide}
