\chapter{MACE}
\label{cha:MACE}

\texttt{MACE} (Machine for Advanced Compiler Education) is a program that simulates the execution of an object file (containing both machine code and data directives) produced as output by an assembler.

Both object file format specification and symbolic assembler are discussed in the assembler documentation.
This document describes the overall internal machine architecture and the supported instruction set.

In the first sections is briefly introduced the internal architecture of the MACE machine. Also the first section introduce the execution steps performed by the machine at run-time.
The last two sections describe the complete instruction set and the encoding format for every instruction.

\section{How MACE works}
\texttt{MACE} execution model is simple.
At first the internal state of the machine is initialized by a bootstrap procedure that works in the following manner:

\begin{itemize}
   \item Test if the object file given as input exists and is readable.
   \item The content of every machine register is set to zero. Thus, \texttt{PC} will point to the first instruction in the code segment.
   \item A block of memory of size 2Kb is reserved and will contain both code and data segment
   \item Machine code is loaded from the object file into the code segment
   \item Data is loaded from the object file into the data segment
\end{itemize}

Once completed the bootstrap procedure the program is ready to be executed.

The execution process works as follows:
\begin{itemize}
   \item Repeat:
   \begin{itemize}
      \item fetch the next instruction according to the value of \texttt{PC}
      \item decode the fetched instruction
      \item execute the instruction
      \item update (if necessary) the content of the register file
      \item update the value of program counter (\texttt{PC})
      \item update the value of the status register (\texttt{PSW})
   \end{itemize}
   \item Until an \texttt{HALT} instruction is encountered.
\end{itemize}


\section{Architecture}
In figure~\ref{fig:images:architecture} is shown the architectural design of the machine simulated by MACE

\begin{figure}[!hbp]
\centering
\resizebox{10cm}{!}
{\includegraphics{mace/architecture}}
\caption{Architectural Design}
\label{fig:images:architecture}
\end{figure}

The architecture is composed by:
\begin{itemize}
   \item 32 General-Purpose 32-Bit registers.
   \item 32-Bit Program Counter (\texttt{PC})
   \item 32-Bit Status Register (\texttt{PSW})
\end{itemize}

\subsection{Data Registers}
The current architecture provides 32 general-purpose registers (\texttt{R0} - \texttt{R31}).
These registers are typically used for word (32 bits) operations. Register \texttt{R0} is always set to 0 (i.e.: even if an instruction tries to assign a value to \texttt{R0}, all the following instructions will always see a value of zero inside the \texttt{R0} location).

\subsection{Program Counter}
The \texttt{PC} contains the address of the instruction currently executing.
During instruction execution, the processor automatically increments the content or places a new value in the \texttt{PC}.

\subsection{Status Register}
The Status Register (\texttt{PSW}) is a 32-Bit register, but only his four lower bits are available in the user mode.
Many integer instructions affect the content of the \texttt{PSW}.
Program instructions also use certain combinations of these bits to control program and system flow.
The first four bits represent a condition of the result generated by an operation.
In the instruction set definitions, the \texttt{PSW} is illustrated as in figure~\ref{fig:images:psw}.

\begin{figure}[!hbp]
\centering
\resizebox{12cm}{!}
{\includegraphics{mace/psw}}
\caption{Status Register}
\label{fig:images:psw}
\end{figure}

The bit `N' (Negative) is set if the most significant bit of the result of an instruction (typically an arithmetic operation) is set to 1; otherwise it is cleared.

The bit `Z' (Zero) is set if the result of an instruction (typically an arithmetic operation) is equal to zero; otherwise it is cleared.

The bit `V' (Overflow) is set only if an arithmetic overflow occurs implying that the result cannot be represented in the operand size.

The bit `C' (Carry) is set if a carry out of the most significant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction.

\section{Addressing Capabilities}
Most operations take a source operand and destination operand, compute them, and store the result in the destination location.
Single-operand operations take a destination operand,compute it, and store the result in the destination location.
External microprocessor references to memory are either program references that refer to program space or data
references that refer to data space.
Program space is the section of memory that contains the program instructions and any immediate data operands residing in the instruction stream.
Data space is the section of memory that contains the program data. Data items in the instruction stream
can be accessed with the program counter relative addressing modes.

\subsection{Instruction Format}
Instructions consist of exactly one word (i.e. 32-bit). Figure~\ref{fig:images:instructions} illustrates the general composition of every type of instruction.

\begin{figure}[!hbp]
\centering
\resizebox{12cm}{!}
{\includegraphics{mace/instructions}}
\caption{Instruction Formats}
\label{fig:images:instructions}
\end{figure}

An instruction specifies the function to be performed with an operation code (i.e. \texttt{opcode}) and defines the
location of every operand.

Possible operands are:
\begin{itemize}
   \item register identifiers.
   \item immediate values
   \item address values
\end{itemize}

The most significant two bits of every instruction (bits 31 and 30) are always set to a value that depends on which is the instruction format. For example, as we can see in figure~\ref{fig:images:instructions} ternary instructions will always have those bits set to `0'.

Every register identifier is defined as a five bit value that represent the general register number.
For example, register R3 will be encoded in the following binary format: `00011'.

Registers can be either directly or indirectly addressed only in ternary instructions.
However, only the destination register \texttt{RDEST} and the second source register \texttt{RSOURCE2} can be indirectly addressed.

In ternary instructions these information are encoded inside the \texttt{flag bits}(the 11 less significant bits of the instruction word).
Flag bits format is shown in figure~\ref{fig:images:fun_bits}.

\begin{figure}[hbp]
\centering
\resizebox{5cm}{!}
{\includegraphics{mace/fun_bits}}
\caption{Function bits}
\label{fig:images:fun_bits}
\end{figure}

If the bit `CARRY' is set to 1, the result of the binary operation between RSOURCE1 and RSOURCE2 is incremented by 1.

If the bit `SIGN' is set to 1, MACE treats the values stored in RSOURCE1 and RSOURCE2 as signed integers.

The bit `INDIRECT\_RDEST' is set to 1 if the destination register is indirectly addressed.

The bit `INDIRECT\_RSOURCE2' is set to 1 if the `RSOURCE2' register is indirectly addressed.

In figure~\ref{fig:images:exampleADD} is shown an example for a \texttt{``ADD (R3) R1 (R2)''} instruction.

\begin{figure}[hbp]
\centering
\resizebox{14cm}{!}
{\includegraphics{mace/exampleADD}}
\caption{An example of encoded ADD instruction}
\label{fig:images:exampleADD}
\end{figure}

\section{Instruction Set}
Instructions are listed by mnemonic.
The information provided about each instruction is: its assembler syntax, its description in words, the effect its
execution has on the condition codes (i.e. the effect on the value stored inside the \texttt{PSW} register), and the addressing modes it may take.

The effect of an instruction on the \texttt{PSW} is specified by the following codes:
\begin{itemize}
   \item \texttt{U} The state of the bit is undefined (i.e., its value cannot be predicted)
   \item \texttt{-} The bit remains unchanged by the execution of the instruction
   \item \texttt{*} The bit is set or cleared according to the outcome of the instruction.
\end{itemize}

the legal source and destination addressing modes are specified by their assembly language
syntax.
The following notation is used when we refers to registers and immediate values:

\begin{itemize}
   \item \texttt{Rn} A Register location.
   \item \texttt{imm} Immediate value which may be 16 bit or 32 bits, depending on the instruction.
\end{itemize}

\subsection{Ternary Instructions}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ADD}               &\emph{Add binary} \\

   \hline
   
   Syntax:           &ADD [Rdest] [RSource1] [RSource2] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] + [RSource2] \\
   Binary Opcode:    &`0000'\\
   &\\
   Description:      &Add the source operand `Rsource1' to `Source2' and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  *  *} \\
                     
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SUB}           &\emph{Subtract binary} \\
   
   \hline
   
   Syntax:           &SUB [Rdest] [RSource1] [RSource2] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] - [RSource2] \\
   Binary Opcode:    &`0001'\\
   &\\
   Description:      &Subtract the source operand `Rsource1' to `Source2' and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes: &\texttt{N   Z   V   C} \\
                    &\texttt{*   *   *   *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ANDL}              &\emph{AND logical} \\
   
   \hline
   
   Syntax            &ANDL [Rdest] [RSource1] [RSource2] \\
   Semantics         &[Rdest] $\leftarrow$ [RSource1].[RSource2] \\
   Binary Opcode:    &`0010'\\
   &\\
   Description:      &Performs an AND between the source operand `Rsource1' and the `Source2' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ORL}          &\emph{OR logical} \\
   
   \hline
   
   Syntax           &ORL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\mid$ $\mid$ [RSource2] \\
   Binary Opcode:    &`0011'\\
   &\\
   Description:      &Performs an OR between the source operand `Rsource1' and the `Source2' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{EORL}           &\emph{Exclusive OR logical} \\
   \hline

   Syntax           &EORL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\oplus$ [RSource2] \\
   Binary Opcode:    &`0100'\\
   &\\
   Description:     &EOR (exclusive or) the source operand `Rsource1' with `Rsource2'
                    and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ANDB}              &\emph{AND bit by bit} \\
   
   \hline
   
   Syntax            &ANDB [Rdest] [RSource1] [RSource2] \\
   Semantics         &[Rdest] $\leftarrow$ [RSource1] $\bigwedge$ [RSource2] \\
   Binary Opcode:    &`0101'\\
   &\\
   Description:      &ANDB the source operand `Rsource1' to the `Rsource2' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ORB}          &\emph{OR bit by bit} \\
   
   \hline
   
   Syntax           &ORB [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\mid$ [RSource2] \\
   Binary Opcode:    &`0110'\\
   &\\
   Description:     &ORB the source operand `Rsource1' to the `Rsource2' operand, and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{EORB}           &\emph{Exclusive OR bit by bit} \\
   \hline

   Syntax           &EORB [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\oplus$ [RSource2] \\
   Binary Opcode:    &`0111'\\
   &\\
   Description:     &EORB (exclusive or) the source operand `Rsource1' with the `Rsource2' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{MUL}            &\emph{MUL binary} \\
   \hline

   Syntax           &MUL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] * [RSource2] \\
   Binary Opcode:    &`1000'\\

   &\\
   Description:     &Multiply the 32-bit `RSource1' operand by the 32-bit `RSource2'
                    operand and store the result in the destination `Rdest'. Both the sources
                    and destination are 32-bit word values. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{DIV}            &\emph{DIV binary} \\
   \hline

   Syntax           &DIV [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] / [RSource2] \\
   Binary Opcode:    &`1001'\\

   &\\
   Description:     &Divide the 32-bit `RSource1' operand by the 32-bit `RSource2'
                    operand and store the result in the destination `Rdest'. Both the sources
                    and destination are 32-bit word values. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SHR}               &\emph{Binary Shift to Right} \\
   \hline

   Syntax           &SHR [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\gg$ [RSource2] \\
   Binary Opcode:    &`1011'\\

   &\\
   Description:     &SHR Performs a binary `shift to right' on the 32-bit `RSource1' operand.
                     The number of bits shifted is stored into the 32-bit `RSource2' operand.
                     The result of the shift operation is stored in the destination register `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SHL}            &\emph{Binary Shift to Left} \\
   \hline

   Syntax           &SHL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\ll$ [RSource2] \\
   Binary Opcode:    &`1010'\\

   &\\
   Description:     &SHL Performs a binary `shift to left' on the 32-bit `RSource1' operand.
                     The number of bits shifted is stored into the 32-bit `RSource2' operand.
                     The result of the shift operation is stored in the destination register `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ROTL}            &\emph{Rotate binary} \\
   \hline

   Syntax           &ROTL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] rotated by $<$[RSource2]$>$ to Left\\
   Binary Opcode:    &`1100'\\
   &\\
   Description:     &Rotate the bits of the operand to the Left. A rotate operation
                     is circular in the sense that the bit shifted out at one end is shifted
                     into the other end. That is, no bit is lost or destroyed by a rotate.
                     Actually the ROTL instruction is not supported by the current architecture; it is
                     translated as a NOP operation \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ROTR}            &\emph{Rotate binary} \\
   \hline

   Syntax           &ROTR [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] rotated by $<$[RSource2]$>$ to Right\\
   Binary Opcode:    &`1101'\\

   &\\
   Description:     &Rotate the bits of the operand to the right. A rotate operation
                     is circular in the sense that the bit shifted out at one end is shifted
                     into the other end. That is, no bit is lost or destroyed by a rotate.
                     Actually the ROTR instruction is not supported by the current architecture; it is
                     translated as a NOP operation \\

   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{NEG}            &\emph{Negate} \\
   \hline

   Syntax           &NEG [Rdest] [RSource1] [RSource2] \\
   Semantics:       &[Rdest] $\leftarrow$ 0 - [RSource2] \\
                    &RSource1 is unused. \\
   Binary Opcode:    &`1110'\\
   &\\
   Description:     &Negate the value of `RSource2' and store the result into
                     `RDest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SPCL}            &\emph{Special opcode} \\
   \hline

   Syntax           &SPCL [Rdest] [RSource1] [RSource2] \\
   Semantics:       &Undefined at the moment. \\
   Binary Opcode:    &`1111'\\

   Description:     &Will be used for future developments \\

   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}

\subsection{Binary Instructions}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ADDI}               &\emph{Add with Immediate operand} \\

   \hline
   
   Syntax:           &ADDI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] + \#[Immediate] \\
   Binary Opcode:    &`0000'\\
   &\\
   Description:      &Add the source operand `Rsource1' to the `immediate' value and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  *  *} \\
                     
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SUBI}           &\emph{Subtract with Immediate operand} \\
   
   \hline
   
   Syntax:           &SUBI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:        &[Rdest] $\leftarrow$ [RSource1] - \#[Immediate] \\
   Binary Opcode:    &`0001'\\
   &\\
   Description:      &Subtract the source operand `Rsource1' to the `immediate' value and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes: &\texttt{N   Z   V   C} \\
                    &\texttt{*   *   *   *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ANDLI}              &\emph{AND with Immediate operand}\\
   
   \hline
   
   Syntax            &ANDLI [Rdest] [RSource1] \#[Immediate] \\
   Semantics         &[Rdest] $\leftarrow$ [RSource1].\#[Immediate] \\
   Binary Opcode:    &`0010'\\
   &\\
   Description:      &Performs an AND between the source operand `Rsource1' and the `Immediate' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ORLI}          &\emph{OR with Immediate operand}\\
   
   \hline
   
   Syntax           &ORLI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\mid$ $\mid$ \#[Immediate] \\
   Binary Opcode:    &`0011'\\
   &\\
   Description:      &Performs an OR between the source operand `Rsource1' and the `Immediate' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{EORLI}           &\emph{Exclusive OR with Immediate operand} \\
   \hline

   Syntax           &EORLI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\oplus$ \#[Immediate] \\
   Binary Opcode:    &`0100'\\
   &\\
   Description:     &EOR (exclusive or) the source operand `Rsource1' with `Immediate'
                    and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ANDBI}              &\emph{AND bit by bit with Immediate operand}\\
   
   \hline
   
   Syntax            &ANDBI [Rdest] [RSource1] \#[Immediate] \\
   Semantics         &[Rdest] $\leftarrow$ [RSource1] $\bigwedge$ \#[Immediate] \\
   Binary Opcode:    &`0101'\\
   &\\
   Description:      &ANDBI the source operand `Rsource1' to the `Immediate' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N  Z  V  C} \\
                     &\texttt{*  *  0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ORBI}          &\emph{OR bit by bit with Immediate operand}\\
   
   \hline
   
   Syntax           &ORBI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\mid$ \#[Immediate] \\
   Binary Opcode:    &`0110'\\
   &\\
   Description:     &ORBI the source operand `Rsource1' to the `Immediate' operand, and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{EORBI}           &\emph{Exclusive OR bit by bit with immediate operand}\\
   \hline

   Syntax           &EORBI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\oplus$ \#[Immediate] \\
   Binary Opcode:    &`0111'\\
   &\\
   Description:     &EORBI (exclusive or) the source operand `Rsource1' with the `Immediate' operand and store the result in the destination location `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V   C} \\
                     &\texttt{*   *   0   0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{MULI}            &\emph{MUL binary with Immediate operand}\\
   \hline

   Syntax           &MULI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] * \#[Immediate] \\
   Binary Opcode:    &`1000'\\

   &\\
   Description:     &Multiply the 32-bit `RSource1' operand by the `Immediate'
                    operand and store the result in the destination `Rdest'. Both the sources
                    and destination are 32-bit word values exception made for the immediate value which
                    is always 16 bit long. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{DIVI}            &\emph{DIV binary with Immediate operand}\\
   \hline

   Syntax           &DIVI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] / \#[Immediate] \\
   Binary Opcode:    &`1001'\\

   &\\
   Description:     &Divide the 32-bit `RSource1' operand by `Immediate'
                    operand and store the result in the destination `Rdest'. Both the sources
                    and destination are 32-bit word values exception made for the immediate value which
                    is always 16 bit long. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SHRI}               &\emph{Binary Shift to Right} \\
   \hline

   Syntax           &SHRI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\gg$ \#[Immediate] \\
   Binary Opcode:    &`1011'\\

   &\\
   Description:     &SHR Performs a binary `shift to right' on the 32-bit `RSource1' operand.
                     The number of bits shifted is given by the value of the Immediate operand `Immediate'.
                     The result of the shift operation is stored in the destination register `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{SHLI}            &\emph{Binary Shift to Left} \\
   \hline

   Syntax           &SHLI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] $\ll$ \#[Immediate] \\
   Binary Opcode:    &`1010'\\

   &\\
   Description:     &SHL Performs a binary `shift to left' on the 32-bit `RSource1' operand.
                     The number of bits shifted is given by the value of the Immediate operand `Immediate'.
                     The result of the shift operation is stored in the destination register `Rdest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ROTLI}            &\emph{Rotate binary} \\
   \hline

   Syntax           &ROTLI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] rotated by $<$\#[Immediate]$>$ to Left\\
   Binary Opcode:    &`1100'\\
   &\\
   Description:     &Rotate the bits of the operand to the Left. A rotate operation
                     is circular in the sense that the bit shifted out at one end is shifted
                     into the other end. That is, no bit is lost or destroyed by a rotate
                     Actually the ROTLI instruction is not supported by the current architecture; it is
                     translated as a NOP operation \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{ROTRI}            &\emph{Rotate binary} \\
   \hline

   Syntax           &ROTRI [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ [RSource1] rotated by $<$\#[Immediate]$>$ to Right\\
   Binary Opcode:    &`1101'\\

   &\\
   Description:     &Rotate the bits of the operand to the right. A rotate operation
                     is circular in the sense that the bit shifted out at one end is shifted
                     into the other end. That is, no bit is lost or destroyed by a rotate
                     Actually the ROTRI instruction is not supported by the current architecture; it is
                     translated as a NOP operation \\

   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{NOTL}            &\emph{Logical complement} \\
   \hline

   Syntax           &NOT [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ ! [RSource1] \\
                    &Immediate is unused. \\
   Binary Opcode:    &`1110'\\
   &\\
   Description:     &Perform a logical NOT operation on the value of `RSource1'.
                     The result is stored into `RDest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{NOTB}            &\emph{Binary complement} \\
   \hline

   Syntax           &NOTB [Rdest] [RSource1] \#[Immediate] \\
   Semantics:       &[Rdest] $\leftarrow$ $\sim$[RSource1] \\
                    &Immediate is unused. \\
   Binary Opcode:    &`1110'\\
   &\\
   Description:     &Perform a binary NOT operation on the value of `RSource1'.
                     The result is stored into `RDest'. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   0  0} \\
   &\\
   &\\
\end{tabular}
\subsection{Unary Instructions}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{NOP}            &\emph{No Operation} \\
   \hline

   Syntax           &NOP \\
   Binary Opcode:    &`0000'\\
   &\\
   Description:     &No Operation performed. This instruction has no effect on the machine internal state \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{MOVA}            &\emph{Move Address to Register Location} \\
   \hline

   Syntax           &MOVA [RDest] [Address] \\
   Semantics:       &[Rdest] $\leftarrow$ [Address] \\
   Binary Opcode:    &`0001'\\
   &\\
   Description:     &Move the value of [Address] into `RDest'. Address is a 20-bit value \\
   Usage:           &MOVA instructions are typically used when we works on address (pointers) or arrays. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{JSR}            &\emph{Jump To Subroutine} \\
   \hline

   Syntax           &JSR [RDest] [Address] \\
   Semantics:       &Jump to the subroutine at address [Address]. Store the return value of the subroutine inside the register `RDest'. \\
   Binary Opcode:    &`0010'\\
   &\\
   Description:     &This instruction implements a jump to subroutine. Actually this opcode is not supported. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{RET}            &\emph{Return from Subroutine} \\
   \hline

   Description:     &RET is not supported by the current architecture. Actually a RET instruction is translated as a HALT instruction. \\
   Binary Opcode:    &`0011'\\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{LOAD}            &\emph{Fill a register with a value read from memory} \\
   \hline

   Syntax           &LOAD [RDest] [Address] \\
   Semantics:       &[Rdest] $\leftarrow$ *[Address] \\
   Binary Opcode:    &`0100'\\
   &\\
   Description:     &Load the value previously stored at `Address' memory location inside the register `Rdest' \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{STORE}            &\emph{Spill a value} \\
   \hline

   Syntax           &STORE [RSource] [Address] \\
   Semantics:       &*[Address] $\leftarrow$ [RSource] \\
   Binary Opcode:    &`0101'\\
   &\\
   Description:     &Store the value of `Rsource' to the `Address' memory location \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{HALT}     &\emph{Halt the machine processor} \\
   \hline

   Binary Opcode:    &`0110'\\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{Scc}            &\emph{Set according to condition `cc'} \\
   \hline

   Syntax           &Scc [Rdest] [Address] \\
   Semantics (pseudo-code):       &IF cc == 1 THEN [Rdest] $\leftarrow$ 1;
                     ELSE [Rdest] $\leftarrow$ 0. \\
                     
   &\\
   Note:            &Condition `cc' is computed starting from
                     the value of the \texttt{PSW} register. For example:
                     instruction `SEQ Rx' stores 1 into Rx if
                     the bit `N' of the status register \texttt{PSW} is set.
                     Otherwise Rx is set to zero.
                     \texttt{C,N,V,Z} refer to the bits of the status register.
                     For example: \texttt{C} refers to the carry bit of the
                     \texttt{PSW} register. \\
                    &Address is unused. \\

\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   &\\
   Possible values for `cc':    &\\
   \textbf{EQ}               &set on equal; \\
   &cc $\leftarrow$ Z \\
   \textbf{GE}               &set on greater than or equal; \\
   &cc $\leftarrow$ N.V + $\overline{N}$.$\overline{V}$ \\
   \textbf{GT}               &set on greater than; \\
   &cc $\leftarrow$ N.V.$\overline{Z}$ + $\overline{N}$.$\overline{V}$.$\overline{Z}$ \\
   \textbf{LE}               &set on less than or equal; \\
   &cc $\leftarrow$ Z + N.$\overline{V}$ + $\overline{N}$.V \\
   \textbf{LT}               &set on less than; \\
   &cc $\leftarrow$ $\overline{N}$.V + N.$\overline{V}$ \\
   \textbf{NE}               &set on not equal; \\
   &cc $\leftarrow$ $\overline{Z}$ \\
   &\\

   Description:      &The specified condition code `cc' is tested. If the condition is true, `Rdest'
                      is set to one; Otherwise `Rdest' is set to zero. \\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   Binary Op-codes:    &\\
   SEQ               &`0111'\\
   SGE               &`1000'\\
   SGT               &`1001'\\
   SLE               &`1010'\\
   SLT               &`1011'\\
   SNE               &`1100'\\
   &\\
   
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{0   *   0  0} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{READ}            &\emph{Read from standard input an integer value} \\
   \hline

   Syntax           &READ [RSource] [Address] \\
   Semantics:       &Read from input an 32-bit signed integer value, and store the value to `RSource'.
                    Address is unused. \\
   Binary Opcode:    &`1101'\\
   &\\
   Description:     &This instruction loads a 32-bit value from standard input into a register.
                     Actually the READ instruction is implemented with a \texttt{scanf}. [See
                     the declaration of `scanf' in the \texttt{stdio.h} header file of the
                     C standard library]. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{*   *   *  *} \\
   &\\
   &\\
\end{tabular}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{WRITE}            &\emph{Write to standard output an integer value} \\
   \hline

   Syntax           &WRITE [RSource] [Address] \\
   Semantics:       &Write to standard output a 32-bit signed integer value stored into Rsource.
                    Address is unused. \\
   Binary Opcode:    &`1110'\\
   &\\
   Description:     &This instruction writes to standard output a 32-bit value.
                     Actually the WRITE instruction is implemented with a \texttt{printf}. [See
                     the declaration of `printf' in the \texttt{stdio.h} header file of the
                     C standard library]. \\
   &\\
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}

\subsection{Jump Instructions}
\begin{tabular}{lp{0.5\textwidth}}
   \textbf{Bcc}            &\emph{Branch on condition cc} \\
   \hline

   \hline

   Syntax           &Bcc [Label] \\
   Semantics (pseudo-code):       &IF cc == 1 THEN \\
                                 & [\texttt{PC}] $\leftarrow$ [\texttt{PC}] + \textbf{Displacement}; \\
                                 &\emph{Displacement} is the distance between the current \emph{\texttt{PC}} and the address associated with the given `Label' \\
                    
                     
   &\\
   Note:            &Condition `cc' is analyzed by taking into consideration
                     the value of the \texttt{PSW} register. For example:
                     instruction `BEQ Label' perform a branch to the instruction
                     labeled `label' if the bit `N' of the status register \texttt{PSW} is set.
                     Otherwise Rx is set to zero.
                     \texttt{C,N,V,Z} refer to the bits of the status register (\texttt{PSW}).
                     For example: \texttt{C} refers to the carry bit of the
                     \texttt{PSW} register. \\

\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   &\\
   Possible values for `cc':    &\\
   \textbf{EQ}               &set on equal; \\
   &cc $\leftarrow$ Z \\
   \textbf{GE}               &set on greater than or equal; \\
   &cc $\leftarrow$ N.V + $\overline{N}$.$\overline{V}$ \\
   \textbf{T}               &branch always. The branch is always `taken'; \\
   \textbf{F}               &This condition is never verified. Thus, branch like this are never `taken'; \\
   \textbf{HI} :            &Branch on higher than \\
   &cc $\leftarrow$ $\overline{C}$.$\overline{Z}$ \\
   \textbf{LS}              &Branch on lower than or same; \\
   &cc $\leftarrow$ C.Z \\
   \textbf{GT}               &set on greater than; \\
   &cc $\leftarrow$ N.V.$\overline{Z}$ + $\overline{N}$.$\overline{V}$.$\overline{Z}$ \\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   \textbf{LE}               &set on less than or equal; \\
   &cc $\leftarrow$ Z + N.$\overline{V}$ + $\overline{N}$.V \\
   \textbf{LT}               &set on less than; \\
   &cc $\leftarrow$ $\overline{N}$.V + N.$\overline{V}$ \\
   \textbf{NE}               &set on not equal; \\
   &cc $\leftarrow$ $\overline{Z}$ \\
   \textbf{CC}              &Branch on carry clear; \\
   &cc $\leftarrow$ $\overline{C}$ \\
   \textbf{CS}              &Branch on carry set; \\
   &cc $\leftarrow$ C \\
   \textbf{VC}              &Branch on overflow clear; \\
   &cc $\leftarrow$ $\overline{V}$ \\
   \textbf{VS}              &Branch on overflow set; \\
   &cc $\leftarrow$ V \\
   \textbf{BPL}             &Branch on plus (i.e. positive);\\
   &cc $\leftarrow$ $\overline{N}$ \\
   \textbf{BMI}             &Branch on minus (i.e. negative);\\
   &cc $\leftarrow$ N \\
\end{tabular}

\begin{tabular}{lp{0.5\textwidth}}
   Description:      &The specified condition code `cc' is tested. If the condition is true,
                      the program counter will be modified in order to point to a specific
                      labeled instruction. \\
   &\\
   Binary Opcodes:    &\\
   BT             &`0000' \\
   BF             &`0001' \\
   BHI            &`0010' \\
   BLS            &`0011' \\
   BCC            &`0100' \\
   BCS            &`0101' \\
   BNE            &`0110' \\
   BEQ            &`0111' \\
   BVC            &`1000' \\
   BVS            &`1001' \\
   BPL            &`1010' \\
   BMI            &`1011' \\
   BGE            &`1100' \\
   BLT            &`1101' \\
   BGT            &`1110' \\
   BLE            &`1111' \\
   &\\
   
   Condition codes:  &\texttt{N   Z   V  C} \\
                     &\texttt{-   -   -  -} \\
   &\\
   &\\
\end{tabular}
